1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, to a method and apparatus for controlling a power-down mode of a delay locked loop (DLL).
2. Discussion of Related Art
A conventional dynamic random access memory (DRAM) memory device has an internal clock system that receives an external clock signal and generates a plurality of different internal clock signals for controlling internal operations of the conventional DRAM memory device using the received external clock signal. An internal clock system of a conventional DRAM memory device is well-known to one of ordinary skill in the art and is a clock domain that is provided by a delay locked loop (DLL) that generates an internal clock signal having a predetermined phase relationship with an external clock signal.
The conventional DRAM memory device is connected to a memory controller that commands read/write operations. Conventionally, the memory controller expects valid data to be loaded on a data bus with a predetermined read latency, that is, after several, for example, seven, external clock cycles from a read command. Accordingly, the conventional DRAM memory device supports a suitable latency using a DLL and a latency counter.
FIG. 1 is a block diagram of a conventional DRAM memory device 100 using a pointer-based latency counter 140.
Referring to FIG. 1, the conventional DRAM memory device 100 includes a command buffer 110, a clock buffer 120, a DLL 130, the pointer-based latency counter 140, a delay compensator 150, and a data output buffer 160. The conventional DRAM memory device 100 receives a read command CMD (READ) through the command buffer 110 and receives an external clock signal EXTCLK through the clock buffer 120. The buffered external clock signal EXTCLK is applied to the DLL 130 to generate an internal clock signal TDLL of the conventional DRAM memory device 100.
The pointer-based latency counter 140 includes a first ring counter 142, a replica delayer 144, a second ring counter 146, and a register 148. The first ring counter 142 receives the internal clock signal TDLL from the DLL 130 to generate first pulse signals TCLK(i), shown in FIG. 2. The replica delayer 144 delays the internal clock signal TDLL by a delay time tSAC+tREAD and transfers the delayed internal clock signal TDLL to the second ring counter 146. The time tSAC denotes a delay time from when the internal clock signal TDLL is generated to when the data DOUT is outputs and the time tREAD denotes a delay time that is taken to transfer the read command READ synchronized with the external clock signal EXTCLK to the pointer-based latency counter 140. The replica delayer 144 includes a replica of circuits on a tSAC path and a replica of circuits on a tREAD path.
The second ring counter 146 receives the delayed internal clock signal from the replica delayer 144 to generate second pulse signals SCLK(i), shown in FIG. 2. In response to the second pulse signals SCLK(i), the register 148 samples and stores a buffered read command READ received from the command buffer 110. In response to the first pulse signals TCLK(i), the register 148 samples the stored read command to generate a latency signal LATENCY.
For a normal latency control operation, the pointer-based latency counter 140 must always maintain the delay time tSAC+tREAD between the first pulse signal TCLK(i) and the second pulse signal SCLK(i). Therefore, a glitch clock pulse must not be inputted into the pointer-based latency counter 140.
In a system using a high-capacity memory device, however, a power-down mode current may affect the system power. In the conventional DRAM memory device 100, most of the current is consumed by the DLL 130 and the pointer-based latency counter 140 during a pre-charge state before entry into a power-down mode. The DLL 130 consumes current by having analog circuits including delay cells and the pointer-based latency counter 140 consumes current by the clock switching of the ring counters. When a glitch clock pulse is inputted into the pointer-based latency counter 140, an error may occur in the latency control. Therefore, the DLL 130 is not allowed to be powered down in a power-down mode of the DRAM. If the DLL 130 is allowed to be powered down in the power-down mode of the DRAM, a power-down current can be greatly reduced. In the DRAM memory device 100 shown in FIG. 1 power down is performed by connecting the DLL 130 to ground under control of power down signal PWR_DN.
FIG. 2 is a timing diagram illustrating an example where an error occurs in the pointer-based latency counter 140 in a power-down exit mode of the DLL 130.
Referring to FIGS. 1 and 2, if the DLL 130 is powered down while the power-down signal PWR_DN has a logic level “LOW”, and then the power-down signal PWR_DN changes into a logic level “HIGH”, the internal clock signal TDLL is generated. The time tSAC and the delay time to of the power-down signal PWR_DN are constant independently of the period of the external clock signal EXTCLK. Accordingly, the power-down signal PWR_DN may not be synchronized with the internal clock signal TDLL. In addition, a glitch clock pulse may occur in the internal clock signal TDLL when the power-down signal PWR_DN changes.
The pulse width of the glitch clock pulse varies according to the frequency of the internal clock signal TDLL. The glitch clock pulse with a predetermined pulse width serves as a count clock pulse in the first ring counter 142. The glitch clock pulse, however, cannot serve as a count clock pulse in the second ring counter 146 when the glitch clock pulse disappears while passing through the replica delayer 144. Accordingly, the delay time between the first pulse signals TCLK(i) and the second pulse signals SCLK(i) becomes different from the intended delay time tSAC+tREAD, which causes an error in the latency signal LATENCY.